Senior Physical Design Engineer

Seeking a highly motivated and innovative Physical Design Implementation Engineer for the Test Chip PHY team.

Does this sound like a good role for you?

The candidate will lead a team of engineers to develop a Test Chip PHY IP for DDR/HBM/UCIe protocols. The position offers an excellent opportunity to work on mixed-signal IPs with focus on digital design.

Tasks will include but not be limited to, RTL synthesis, creating floor plans, running Place & Route/CTS flows using Synopsys tools, checking design equivalency, performing Static Timing Analysis and timing closure ECOs, constraints development, static and dynamic IR drop analysis, power estimation, electromigration checks and other verifying the test-chips for DRC/LVS/ERC/PERC checks.

Additional tasks will include creation of views necessary for Test Chip tapeout, conducting mock tapeouts and running all required QA checks before release of these views. The candidate will work independently to find solutions to complex design implementation issues and to suggest improvements to the design methodology and design flows

Key Requirements

• Requires a degree in Electrical/Electronics Engineering (or equivalent) and 10+ years working experience in a related field.
• Previous experience of leading a project as Technical Lead.
• Previous experience with Physical Design of SOCs or IPs with ability to handle broad responsibility from RTL to signoff of Digital ASIC designs.
• Prior knowledge and experience with state-of-the-art CAD tools (DC, PT, ICC2/FC, ICV) and technologies (FinFet) is required.
• Previous experience of working with RTL synthesis, SDCs and timing signoff using PTSI
• Experience with solving Physical Verification (DRC, LVS, Antenna, etc) violations, understanding of DFT implementation techniques, resolving signal and power integrity faults.
• Ability to resolve a wide range of issues in creative ways
• Excellent communication skills, verbal and written